(1) Field of the Invention
The present invention relates to the field of integrated circuit design. More specifically, the present invention relates to verification techniques of asynchronous designs.
(2) Background Technology
FIG. 1 represents a synthesis based high level flow diagram of a prior art process for design, capture and verification of an integrated circuit (IC) design. The present invention relates to methods and systems for design verification. An overall process is discussed below as background.
The process starts at block 10 where the IC design is specified and basic performance goals such as clock speed and signal throughput are defined. At block 12, high level block planning is performed where the IC design is partitioned into major functional units or blocks, each block can be allocated an area goal and also a delay or power consumption budget. At block 14, the design is captured by a designer into a hardware description language (HDL), such as Verilog or VHDL. This language description of the IC circuit is represented as block 16. At block 20, the HDL description 16 runs through a functional simulator to verify its functionality. If needed, modifications to the HDL are performed at block 18 such that the HDL description 16 meets its expected functionality.
At block 22, logic synthesis procedures take the HDL 16 and perform logic synthesis to translate the HDL into generic operators and then the generic operators are mapped into a technology dependent netlist having defined components (e.g., cells) and interconnections between them. Logic synthesis 22 procedures generate a gate-level representation of the IC design also called a mapped netlist. As a result of analysis to be described below, logic optimizations are performed to optimize the gate-level representation to certain performance and or design rule constraints and other design objectives.
At block 26 of FIG. 1, static timing analysis is performed which analyzes the timing characteristics of the mapped netlist to verify certain timing requirements. If timing violations exist or the design goals have not been achieved, timing constraints are re-adjusted and various synthesis directives and techniques are used to optimize the design accordingly. Modifications to the design can require generation of an amended HDL description 16 and another logic synthesis 22. At block 24, a gate-level simulation is performed to verify correct functionality after technology mapping and transformations are performed. Block 24 also checks for consistency with the behavior and register transfer level simulation. The gate-level simulation 24 ("full timing" simulation) can be unit delay based (where each cell is assumed to have a one unit delay associated therewith and a unit propagation delay between cells is assumed), or preferably can be a cycle based (where the cells are analyzed at the clock transitions) for best simulation performance. Full timing simulation 24 may be required for asynchronous parts of the design to verify timing correctness.
At block 28, the design is floorplanned, placed and routed, typically using the physical and timing constraints generated from previous states. At block 30, more accurate cell and net delays are calculated based on wire topology. These can be back-annotated into logic synthesis block 22, the static timing analysis block 26, and the gate-level simulator 24, for more realistic verification or optimization of the design.
At block 32 of FIG. 1, timing verifications are performed to verify that the final design satisfies the given or determined performance constraints (e.g., timing). Logic simulation 34 can also be performed to verify functional and timing aspects of the design. Block 36 monitors the output of blocks 32 and 34 to determine of the design satisfies the timing and functional requirements. If so, the prior art process of FIG. 1 reports the verification status.
FIG. 2 illustrates input and output signals to a full-timing event driven simulator ("logic simulator") 248 that operates on the gate-level to verify the timing and functionality of IC designs. In full-timing event driven simulation 248, the functionality and timing behavior of the design are verified by sensitizing the circuit using a set of test vectors that are applied to the design's primary inputs (usually coupled to an input pad). Simulation libraries 240 that are technology specific are input to the logic simulator 248. Test vectors 242 (patterns) are also input to the simulator 248 as well as a gate-level design description ("netlist") 244 that describes the design portion or block to be verified. A simulation control file 246 is input that sets up certain simulation parameters and design constraints and the logic simulator 248 generates a simulation report 250 in response to the above.
A major limitation to the above approach is that the quality of the timing verification process is very much dependent on the completeness of the test vectors, as only those paths sensitized by the test vectors are checked for timing violations by the simulator 248. Test vectors 242 designed for the design description 244 should be extensive and well conceived. Further, since the logic simulator 248 operates at the gate-level, performing both timing and functionality verification, it consumes a relatively large amount of processing time and therefore is impractical for verification of million-gate and larger designs.
FIG. 3 illustrates another method for verifying the timing of digital electronics circuits by use of a static timing analyzer 264. Process 264 examines the timing properties of every path in the design independent of its functionality. As a result, the analysis is exhaustive and complete. Process 264 inputs timing and logic libraries 260 that are technology dependent and also the design description 262 which describes the design region to be verified. A control file 266 is input and a verification report 268 is generated by the static timing analyzer 264. Aside from its exhaustiveness, the static timing analyzer 264 also offers much faster processing speed over the logic simulator 248. As a result, the static analyzer 264 is becoming more popular with the larger and more complex VLSI circuits for performing timing verification. This is causing a change in the way the timing and functionality of a design are verified.
FIG. 4A illustrates that for a fully synchronous design, static timing verification 276 can be used after synthesis 274, while a functional simulation 272 can be performed on the HDL 270 before synthesis 274 at the Register Transfer (RT) level. Static timing analysis 276 is best suited for synchronous designs where all signal events are measured with respect to a reference clock. Using the flow shown in FIG. 4A, the design described in the HDL 270 is verified for functionality by the functional simulation 272 and the static timing verification 276 is performed to verify the timing behavior of the design.
FIG. 4B illustrates the verification process used for an asynchronous design defined by HDL 280 that also contains synchronous regions. A functional simulation is performed 282 (ignores timing aspects) and then synthesis is performed at 284. For designs that are partly asynchronous, the timing correctness of the design can no longer be verified only through static timing analysis. For this kind of design 280, the entire circuit design or its asynchronous regions have to be timing simulated at the gate-level. For asynchronous designs, timing and functionality need to be verified simultaneously, as the circuit behavior on the functional level can be altered by the timing characteristics of the circuit.
Although effective in some applications, the approach of FIG. 4B has several drawbacks in certain circumstances. First, if the entire design needs to be timing simulated, then the major advantages (e.g., exhaustiveness and speed) of using a static timing analyzer 286 are lost. Secondly, if only selected portions of the IC design need to be analyzed, then the designer is faced with the challenge of identifying and isolating the asynchronous regions and creating the proper test vectors to apply to these regions. However, creating the test vectors is difficult because the regions may or may not correspond to a well defined module within the entire IC design and/or the asynchronous regions may or may not have well defined functionality. In the face of these challenges, the designer is required to generate test vectors to exercise each asynchronous region with a reasonable degree of completeness.
What is needed is a system and method that can readily determine and apply a set of test vectors for isolated asynchronous regions of the design in a full-timing gate-level simulation while allowing static timing verification to operate on the synchronous regions of the design. The present invention provides this advantageous functionality.
Accordingly, it is desired to provide a method and system for verifying timing and functionality of IC designs that include synchronous and asynchronous regions. It is further desired to provide the above within a system that automatically determines the boundaries between the synchronous and asynchronous design regions, and that automatically determines test vectors to apply to the asynchronous regions. It is further desired to provide the above wherein static timing verification can be advantageously applied to verify synchronous regions of the IC design while full timing gate-level simulation can be applied only to those asynchronous regions of the design for timing and functionality verification. The present invention offers the above advantageous functionality while providing an automatic, computer controlled method and system for generating the required test vectors in a system for verification of the asynchronous regions of the IC design. These and other advantages of the present invention not specifically described above will become clear within discussions of the present invention herein.